电气工程学院
首页  人员信息
陈乃金
发布人:刘丙友  发布时间:2018-09-30   动态浏览次数:1013

1、基本信息:

  

陈乃金,男,安徽合肥人,教授,硕士生导师,校学术骨干,CCF容错专委。

联系方式: 86naijinchen@tongji.edu.cnQQ3091271353

  

2、教育经历:

  

2013年毕业于同济大学,获工学博士学位;2016年博士后出站于天津大学,获博士后证书。

  

3、主要研究方向:

  

时域划分与映射,可重构与容错计算,VLSI设计、测试与验证,可信计算与NOC网络,语义大数据表示和推理、存储、调度,EDA设计及自动化,数据挖掘与最优化问题求解,算法设计与形式化分析。

  

4、科学研究:

  

近年来主持安徽省高校省级自然科学研究重点项目、安徽省自然科学基金项目、芜湖市科技计划项目10余项,作为骨干参加国家863项目2项,国家重点研发计划项目1项,国家自然科学基金重点项目1项。

  

5、科研成果:

以第一作者发表学术论文30余篇,授权软件著作权和发明专利10项,代表性的论文列举如下:

  

[01]  Chen Naijin, Feng Zhiyong, Jiang Jianhui, He Ruixiang, Wang Zhen.  Pipeline

Mapping Performance Evaluation for Row Parallel Reconfigurable Cell Array. [J].Journal

of Tongji University(Natural Science), 2017, 45(8): 1218-1226.(EI)

[02] Chen NaijinFeng Zhiyong.Interconnect Delay Performance Evaluation for Non-Crossing Leveland Row Operands Parallel RCA[J].Journal of Tianjin University(Science and Technology),2017,50(4):429-436. (EI)

[03] Chen Naijin,Jiang Jianhui.Mapping Algorithm of Coarse Grained Reconfigurable Cell Array for Multibranch Tree Data Flow Graph[J].Journal of Computer-Aided Design & Computer Graphics. 2016,28(7):756-766.(EI)

[04] Chen Naijin,Jiang Jianhui. Considering Communication-Cost and Hardware-Fragment Utilization Cluster Partitioning Algorithm[J].Journal of Computer-Aided Design & Computer Graphics. 2015,27(4):754-763.(EI)

[05] Chen Naijin,Jiang Jianhui.A Multi-Objective Optimization Mapping Algorithm for Coarse Grained Reconfigurable Architectures[J].Chinese Journal of Electronics. 2015, 43 (11):2151-2160.(EI)

[06] Chen Naijin, Feng Zhiyong, Jiang Jianhui.Bypass node non-redundant adding algorithm for crossing-level data transmission in two-dimension reconfigurable cell array[J].Journal on Communications.2015,36(4):2015132:1-17. (EI)

[07]Chen Naijin, Jiang Jianhui. Hardware-task partitioning algorithm merged area estimation with multi-objective optimization[J].Journal on Communications, 2013,34(2):40-55. (EI)

[08]Chen Naijin,Jiang Jianhui,Chen Xin,Zhou Zhou,Xu Yin.An Improved Level Partitioning Algorithm Considering Minimum Execution Delay and Resource Restraints[J].Chinese Journal of Electronics. 2012,40(5):1055-1066.(EI)

[09] Naijin Chen, Jianghui Jiang. Mapping algorithm for coarse-grained  reconfigurable multimedia architectures.IEEE International Parallel&& istributed Processing Symposium (IPDPS), Shanghai, IEEE CS Press, Shanghai, China, 2012, pp. 281-286.(EI, CCF-B)

[10] Wang Zhen, Jiang Jianhui, Chen Naijin, Lu Guangming, Zhang Ying. Effects of Thee Factors Under BTI on the Soft Error Rate of Integrated Circuits. [J].Journal of Computer Research and Development, 2018, 55 (5): 1108-1116. (EI)

[11] Wang Zhen, Jiang Jianhui, Chen Naijin. BiasTemperature Instability-aware Soft Error

Rate Analysis. [J].Journal of Electronics & Information Technology, 2017, 39 (7): 1640-1645.(EI)